Power conversion apparatus

ABSTRACT

A controller outputs pulse signals to a first switch and a second switch based on a circuit current flowing through a power conversion circuit and a voltage of an AC power supply. The first switch is opened and closed alternately to the second switch. According to the opening and closing, a current in which a high frequency component is mixed with a low frequency component of the AC power supply flows through the power conversion circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2013-165469, filed Aug. 8, 2013, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a power conversionapparatus that converts an alternating current voltage obtained from anAC power supply to a direct current voltage and supplies the electricpower to a load.

BACKGROUND

In the related art, as a method of converting the alternating currentvoltage to the direct current voltage, two following methods aregenerally known.

The first method uses a diode bridge circuit and a smoothing capacitor.The diode bridge circuit performs full wave rectification on thealternating current from the AC power supply. The smoothing capacitorsmoothes the direct current after the full wave rectification.

In the first method, even if the alternating current voltage is eitherpositive or negative, the current always flows through a series circuitof two diodes. At this point, in two diodes, the electric powercorresponding to the product of the current flowing through the diodeand the voltage in a forward direction of the diode is lost.

In the second method, a power factor improvement converter (PFC) isinterposed between the diode bridge circuit and the smoothing capacitorin the first method. The power factor improvement converter boosts thevoltage of the direct current subjected to the full wave rectificationin the diode bridge circuit.

In the second method, since the current flows through a series circuitof two diodes at the time of the full wave rectification, the electricpower is also lost. In addition, since the current flows alternatelythrough a field effect transistor (FET) configuring the power factorimprovement converter and the diode, the electric power is further lost.

Additionally, in order to cause the waveform of the input current to bea sine wave, the power factor improvement converter is required to setthe output voltage to be higher than the input voltage. However, theexemplary embodiments are not limited to the configuration in which thevoltage required in the load is necessarily higher than the inputvoltage. In this case, a step-down converter is connected to thedownstream of the power factor improvement converter. Then, the voltageboosted by the power factor improvement converter is stepped-down to adesired voltage. When stepping-down, the electric power is also lost.The entire power conversion apparatus has a three-stage configuration ofthe AC-DC conversion, the DC-DC (step-up) conversion, the DC-DC(step-down) conversion, and the electric power loss is shown as theproduct of these conversions. For example, if the efficiency for onestage is 0.95, the efficiency for three stages is 0.95×0.95×0.95=0.86.That is, even in the prominent conversion having 95% efficiency, theefficiency falls to 86% in a three-stage connection. In this manner,even if each of the conversion efficiencies is good, the conversionefficiency remarkably deteriorates by setting the conversion to be multistage.

Recently, the public demand for power saving properties of electricapparatus is increased. At the same time, it is essential not to producecurrent harmonic noises so as not to negatively influence the externalenvironment. Therefore, the compatibility of the conversion efficiencyenhancement and the current harmonics suppressing function in the powerconversion apparatus that supplies the electric power to the load isdemanded.

JP-A-2007-110869 and JP-A-2008-295248 are examples of the related art.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a configuration of a circuit of a powerconversion apparatus according to a first embodiment.

FIG. 2 is a diagram illustrating waveforms of a main current flowingthrough the power conversion circuit according to the first embodiment.

FIG. 3 is a diagram illustrating waveforms for describing an envelopegeneration process according to the first embodiment.

FIG. 4 is a block diagram illustrating a specific configuration of acontroller according to the first embodiment.

FIG. 5 is a diagram illustrating waveforms for describing the operationof the controller according to the first embodiment.

FIG. 6 is a block diagram illustrating a specific configuration of acontroller according to a second embodiment.

FIG. 7 is a diagram illustrating waveforms for describing the operationof the controller according to the second embodiment.

FIG. 8 is a diagram illustrating a circuit configuration of a powerconversion apparatus according to a third embodiment.

FIG. 9 is a block diagram illustrating a specific configuration of acontroller according to the third embodiment.

FIG. 10 is a diagram illustrating waveforms for describing an operationof the power conversion apparatus according to the third embodiment.

FIG. 11 is a block diagram illustrating a specific configuration of acontroller according to a fourth embodiment.

FIG. 12 is a diagram illustrating waveforms for describing an operationof a power conversion apparatus according to the fourth embodiment.

FIG. 13 is a diagram illustrating a circuit configuration of a powerconversion apparatus according to a fifth embodiment.

FIG. 14 is a block diagram illustrating a specific configuration of acontroller according to the fifth embodiment.

FIG. 15 is a block diagram illustrating a specific configuration of acontroller according to a sixth embodiment.

FIG. 16 is a diagram illustrating waveforms in an example in whichimbalance between capacitance voltages of a first capacitor and a secondcapacitor is generated according to the sixth embodiment.

FIG. 17 is a diagram illustrating waveforms for describing acompensation process when imbalance between capacitance voltages of thefirst capacitor and the second capacitor is generated according to thesixth embodiment.

FIG. 18 is a diagram illustrating waveforms for describing acompensation process when imbalance between capacitance voltages of thefirst capacitor and the second capacitor is generated according to thesixth embodiment.

FIG. 19 is a block diagram illustrating a specific configuration of acontroller according to a seventh embodiment.

FIG. 20 is a diagram illustrating waveforms for describing an operationof the controller according to the seventh embodiment.

DETAILED DESCRIPTION

An object of the embodiments is to achieve the compatibility of theconversion efficiency enhancement and the current harmonics suppressingfunction in the power conversion apparatus that supplies the electricpower to the load.

According to an aspect of the embodiment, a power conversion apparatusincludes a power conversion circuit, a circuit current detectionportion, a supply voltage detection portion, and a control portion.

The power conversion circuit includes a path configured to form a closedloop by connecting a first switch and a second switch in series,connecting a first capacitor and a second capacitor in series,connecting the first switch and the second switch respectively to thefirst capacitor and the second capacitor, to connect a connection pointbetween the first switch and the second switch and a connection pointbetween the first capacitor and the second capacitor through a seriescircuit of an AC power supply, a low pass filter, an inductor, and aload, and to bypass the AC power supply and the low pass filter.

The circuit current detection portion detects a circuit current thatflows through the power conversion circuit.

The supply voltage detection portion detects a voltage of the AC powersupply.

The control portion outputs pulse signals for alternately opening andclosing the first switch and the second switch to the first switch andthe second switch based on the circuit current detected by the circuitcurrent detection portion and a supply voltage detected by the supplyvoltage detection portion so that a current in which a high frequencycomponent is mixed with a low frequency component of the AC power supplyflows through the power conversion circuit.

Hereinafter, embodiments of a power conversion apparatus are describedwith reference to the drawings.

First Embodiment

FIG. 1 is a diagram illustrating a configuration of a circuit of a powerconversion apparatus 1-1 according to a first embodiment. The powerconversion apparatus 1-1 includes a power conversion circuit 11-1 and acontroller (control portion) 12-1 thereof.

The power conversion circuit 11-1 includes first and secondsemiconductor switches (hereinafter, simply referred to as switches) S1and S2, first and second smoothing capacitors (hereinafter, simplyreferred to as capacitors) C1 and C2, an inductor L1, a low pass filterLPF, and a high pass filter HPF. The first and second switches S1 and S2all use N-channel MOS field effect transistors (MOSFET).

In the power conversion circuit 11-1, a source terminal of the firstswitch S1 is connected to a drain terminal of the second switch S2.Additionally, the first capacitor C1 and the second capacitor C2 areconnected in series. Further, a terminal of the first capacitor C1 whichis not connected to the second capacitor C2 is connected to a drainterminal of the first switch S1, and a terminal of the second capacitorC2 which is not connected to the first capacitor C1 is connected to asource terminal of the second switch S2.

In the power conversion circuit 11-1, an AC power supply E is connectedto a connection point between the first switch S1 and the second switchS2, and the low pass filter LPF is connected to the AC power supply E inseries. Further, a load M is connected to the low pass filter LPF inseries, and the load M is connected to the connection point between thefirst capacitor C1 and the second capacitor C2. Additionally, in thepower conversion circuit 11-1, a high pass filter HPF is connected to aseries circuit between the AC power supply E and the low pass filter LPFin parallel.

Therefore, the power conversion circuit 11-1 forms a first closed loopcircuit 111 including the parallel circuit between the high pass filterHPF and the series circuit between the AC power supply E and the lowpass filter LPF, the inductor L1, the load M, the first capacitor C1,and the first switch S1, and a second closed loop circuit 112 includingthe parallel circuit, the inductor L1, the load M, the second capacitorC2, and the second switch S2.

The power conversion apparatus 1-1 includes a circuit current detectionunit (circuit current detection portion) 13 that detects a circuitcurrent Is of the power conversion circuit 11-1, and a supply voltagedetection unit (supply voltage detection portion) 14 that detects asupply voltage Vin of the power conversion circuit 11-1. The circuitcurrent detection unit 13 is interposed between the connection pointbetween the first switch S1 and the second switch S2 and the connectionpoint between the AC power supply E and the high pass filter HPF, anddetects the circuit current Is that flows through the first and secondclosed loop circuits 111 and 112. The supply voltage detection unit 14is connected to the AC power supply E in parallel, and detects thevoltage yin of the AC power supply E.

The circuit current detection unit 13 provides the detected circuitcurrent Is to the controller 12-1. The supply voltage detection unit 14also provides the detected supply voltage Vin to the controller 12-1.

The controller 12-1 generates first and second pulse signals P1 and P2for causing the first switch S1 and the second switch S2 to performswitching operations, based on the circuit current Is and the supplyvoltage Vin. Then, the controller 12-1 supplies the first pulse signalP1 to a gate terminal of the first switch S1, and the second pulsesignal P2 to a gate terminal of the second switch S2.

The first switch S1 is conducted while the first pulse signal P1 issupplied to the gate terminal. If the first switch S1 is conducted, thecircuit current Is flows through the first closed loop circuit 111. Thesecond switch S2 is conducted while the second pulse signal P2 issupplied through the gate terminal. If the second switch S2 isconducted, the circuit current Is flows through the second closed loopcircuit 112.

According to the embodiment, the commercial power supply of 100 V[Volt]/50 Hz [Hertz] is used as the AC power supply E. Then, thecontroller 12-1 generates the first pulse signal P1 and the second pulsesignal P2 so that a high frequency component of 100 KHz is mixed in thecircuit current Is of 50 Hz generated from the AC power supply E.

FIG. 2 is a diagram illustrating waveforms of a main current flowingthrough the power conversion circuit 11-1. In FIG. 2, a waveform Waindicates the circuit current Is detected by the circuit currentdetection unit 13. A waveform Wb indicates a current passing through thelow pass filter LPF. A waveform We indicates a current passing throughthe high pass filter HPF. As illustrated in FIG. 2, a current of a lowfrequency component (50 Hz) passing through the low pass filter LPF anda current of the high frequency component (100 KHz) passing through thehigh pass filter HPF are mixed in the circuit current Is. Also, only thecurrent of the low frequency component (50 Hz) passes through the ACpower supply E of the parallel circuit by an operation of the low passfilter LPF. Meanwhile, only the current of the high frequency component(100 Hz) passes through the high pass filter HPF by an operation of thehigh pass filter HPF. Therefore, two kinds of alternating currentshaving different frequencies are mixed and operate in the entire powerconversion circuit 11.

The current of the high frequency component (100 KHz) is obtained byalternately opening and closing the first switch S1 and the secondswitch S2 at a high speed. For this, the first switch S1 and the secondswitch S2 may be alternately switched so that a pair of positive andnegative sinusoidal envelopes that define peaks of the circuit currentIs are generated, and directions of the current are switched between theenvelopes. The process is described with reference to FIG. 3.

A waveform Wd of FIG. 3 indicates the supply voltage Vin. In the case ofthe AC power supply E, the supply voltage Vin changes in a sinusoidalmanner. If the AC power supply E is a commercial power supply of 100 V,the waveform of the supply voltage Vin detected by the supply voltagedetection unit 14 becomes a sine wave in which the positive peak valueis 141 V and the negative peak value is −141 V as indicated in thewaveform Wa. Here, according to the embodiment, sinusoidal envelopes arecreated based on the waveform of the supply voltage Vin.

Here, it is assumed that in the power conversion apparatus 1-1, electricpower of 200 W [Watt] is supplied from the AC power supply E of 100 V tothe load M. In this case, the supply voltage is 100 V. Accordingly, ifan input current of 2 A [Ampere] in the same cycle with the supplyvoltage is obtained, the electric power of 200 W [Watt] is supplied fromthe AC power supply E of 100 V to the load M.

A waveform We of FIG. 3 indicates a sinusoidal current waveform of 2 Ain the same cycle with the supply voltage. As illustrated in the figure,the positive peak value of the waveform is 2.82 A, and the negative peakvalue is −2.82 A. That is, a value obtained by multiplying the supplyvoltage Vin by the coefficient k=0.02 becomes a target current value It.

A waveform Wf of FIG. 3 indicates sinusoidal envelopes (current peaktarget value) required as a standard for switching the directions of thecircuit current Is. The envelopes include a positive envelope +e fordeciding a standard for switching the positive direction of the circuitcurrent Is, and a negative envelope −e for deciding a standard forswitching the negative direction of the circuit current Is. The positiveenvelope +e is generated by adding the width d to the target currentvalue It. The negative envelope −e is generated by subtracting the widthd from the target current value It. The width d is a value obtained byadding some margins to the negative (positive) peak value of thepositive (negative) envelope +e (−e). This is because when the currentvalue is negative (positive), the current value leaves envelop on thepositive (negative) side.

The waveform We has the positive peak value of 2.82 A and the negativepeak value of −2.82 A. If the waveform We is the target current valueIt, the width d is, for example, “3”. Accordingly, when the current ison the negative peak, the positive envelope +e is 0.18 (=−2.82+3), andthe envelope +e can be maintained on the positive region. In the samemanner, when the current is on the positive peak, the negative envelope−e is −0.18 (=2.82−3), and the envelope −e can be maintained on thenegative region.

When the circuit current Is reaches the positive envelope +e and reachesthe negative envelope −e, the controller 12-1 generates the first pulsesignal P1 and the second pulse signal P2 so that the opening and theclosing of the first switch S1 and the second switch S2 are in reverse.Then, as illustrated in a waveform Wg, in the circuit current Is, thehigh frequency component (100 KHz) generated by the opening and theclosing of the first switch S1 and the second switch S2 is mixed to thelow frequency component (50 Hz) in the same cycle with the supplyvoltage. In addition, the frequency of the high frequency component isnot fixed, and determined by the positive and negative envelopes +e and−e.

FIG. 4 is a block diagram illustrating a specific configuration of thecontroller 12-1. The controller 12-1 includes a current target valuedecision unit 121, an envelope generation unit 122, an upperdetermination unit 123, a lower determination unit 124, and a latchcircuit 125.

The current target value decision unit 121 receives a signal of thesupply voltage Vin detected by the supply voltage detection unit 14 asan input, and multiplies a predetermined coefficient k by the signal,and decides the target current value It. Then, the current target valuedecision unit 121 supplies a signal corresponding to the current valueIt to the envelope generation unit 122 (decision portion).

The envelope generation unit 122 generates the positive envelope +e byadding the width d to the signal corresponding to the current value It.Additionally, the envelope generation unit 122 generates the negativeenvelope −e by subtracting the width d from the signal corresponding tothe current value It. Then, the envelope generation unit 122 supplies asignal corresponding to the positive envelope +e to a first inputterminal of the upper determination unit 123, and a signal correspondingto the negative envelope −e to a first input terminal of the lowerdetermination unit 124 (envelope generation portion).

The signals of the circuit current Is detected by the circuit currentdetection unit 13 is supplied to the respective second input terminalsof the upper determination unit 123 and the lower determination unit124. Since the upper determination unit 123 determines whether thecircuit current Is between the envelopes, that is, between the positiveenvelope +e and the negative envelope −e comes into contact with thepositive envelope +e when the circuit current Is rises, a trigger signalTr1 is supplied to the first input terminal of the latch circuit 125whenever the contact is detected. Since the lower determination unit 124determines whether the circuit current Is between the envelopes comesinto contact with the negative envelope −e when the circuit current Isfalls, a trigger signal Tr2 is supplied to the second input terminal ofthe latch circuit 125 whenever the contact is detected (determinationportion).

When the trigger signal Tr1 is input to the first input terminal, thelatch circuit 125 maintains a state in which the first pulse signal P1is “0”, and the second pulse signal P2 is “1”. Additionally, when thetrigger signal Tr2 is input to the second input terminal, the latchcircuit 125 maintains a state in which the first pulse signal P1 is “1”,and the second pulse signal P2 is “0” (pulse generation portion).

FIG. 5 is a diagram illustrating signal waveforms for describing theoperation of the controller 12-1. A waveform Wh enlarges and illustratesa relationship between the circuit current Is and the positive envelope+e and the negative envelope −e generated in the envelope generationunit 122. A waveform Wi indicates the trigger signal Tr1 output from theupper determination unit 123. A waveform Wj indicates the trigger signalTr2 output from the lower determination unit 124. A waveform Wkindicates the first pulse signal P1 output from the latch circuit 125. Awaveform W1 indicates the second pulse signal P2 output from the latchcircuit 125.

As illustrated in FIG. 5, if the circuit current Is that fluctuatesbetween the envelopes comes in contact with the positive envelope +e(time points t1, t3, t5, t7, and t9), the first trigger signal Tr1 isoutput. Then, the first pulse signal P1 becomes “0”, and the secondpulse signal P2 becomes “1”, so that the state is maintained. As aresult, the second switch S2 is blocked, and the first switch S1 isopen, so the circuit current Is switched to decrease.

Thereafter, if the circuit current Is comes into contact with thenegative envelope −e (time points t2, t4, t6, and t8), the secondtrigger signal Tr2 is output. Then, the first pulse signal P1 becomes“1”, and the second pulse signal P2 becomes “0”, so that the state ismaintained. As a result, the first switch S1 is blocked, and the secondswitch S2 is open, so the circuit current Is is switched to rise.

Therefore, the circuit current Is reciprocates between the envelopes, sothat rise and fall are repeated. Then, if the circuit current Isreciprocates, the first switch S1 and the second switch S2 arealternately switched. As a result, the circuit current Is in which thehigh frequency component (100 KHz) is mixed with the low frequencycomponent (50 Hz) of the AC power supply E flows through the powerconversion circuit 11-1, and supplied to the load M. At this point,since only the low frequency component passing through the low passfilter LPF flows through the AC power supply E, the high frequencycomponent does not leak to the outside.

According to the first embodiment as described above, it is possible togenerate the sinusoidal current waveform identical to the supply voltagewaveform by the power conversion circuit 11-1 having a simple circuitconfiguration and the controller 12-1 having a simple functionalconfiguration. The possibility of generating the sinusoidal currentwaveform identical to the supply voltage waveform means to have afunction of suppressing current harmonic. That is, it is veryadvantageous in the industry since it is possible to provide the powerconversion apparatus 1-1 including the function of suppressing currentharmonics at a low cost.

Additionally, if the load M is driven as an inverter, it is possible toconvert the AC power supply E into a high frequency alternating currentonly by 1 step, and also it is possible to cause the width to the highfrequency alternating current to be always constant regardless of thelow frequency phase of the supply voltage. In this manner, thepossibility of the conversion by 1 step means that extremely highlyeffective electric power conversion is possible, and the industrialeffect is significant. Further, since constant electric power can besupplied to the load M, even if a circuit is simple, a constantoperation can be realized.

Second Embodiment

In the first embodiment, since the first pulse signal P1 and the secondpulse signal P2 are simultaneously switched, there is a danger ofswitching on the first switch S1 and the second switch S2 at the sametime at the moment of switching. In order to avoid the danger, a delaytime (dead time) At is provided when the first pulse signal P1 and thesecond pulse signal P2 are switched so that the first switch S1 and thesecond switch S2 are not turned on at the same time according to asecond embodiment.

FIG. 6 is a block diagram illustrating a specific configuration of acontroller 12-2 of a power conversion apparatus 1-2 according to thesecond embodiment. Portions common to the controller 12-1 according tothe first embodiment are denoted by the same reference numerals, and thedetailed descriptions thereof are omitted. Additionally, since a powerconversion circuit 11-2 is the same with that in the first embodiment,the description thereof is omitted here.

The controller 12-2 includes a dead time generation unit 126 in additionto the current target value decision unit 121, the envelope generationunit 122, the upper determination unit 123, the lower determination unit124, and the latch circuit 125. The dead time generation unit 126 inputsa pulse signal P0 output from the latch circuit 125. Then, the dead timegeneration unit 126 generates the first pulse signal P1 and the secondpulse signal P2 according to the pulse signal P0, and supplies the firstpulse signal P1 and the second pulse signal P2 respectively to the firstand second switches S1 and S2.

FIG. 7 is a diagram illustrating a signal waveform for describing theoperation of the dead time generation unit 126. A waveform Wm indicatesthe trigger signal Tr1 output from the upper determination unit 123. Awaveform Wn indicates the trigger signal Tr2 output from the lowerdetermination unit 124. A waveform Wo indicates the pulse signal P0output from the latch circuit 125. A waveform Wp indicates the firstpulse signal P1 output from the dead time generation unit 126. Awaveform Wq indicates the second pulse signal P2 output from the deadtime generation unit 126.

As illustrated in FIG. 7, when the trigger signal Tr2 is input, thelatch circuit 125 maintains a state in which the pulse signal P0 is “1”.Additionally, when the trigger signal Tr1 is input, the latch circuit125 maintains a state in which the pulse signal P0 is “0”.

When the pulse signal P0 is “1”, the dead time generation unit 126maintains a state in which the second pulse signal P2 is “0”. Then, ifthe predetermined delay time At passes after the pulse signal P2 is “0”,the dead time generation unit 126 maintains a state in which the firstpulse signal P1 is “1”. Additionally, if the pulse signal P0 becomes“0”, the dead time generation unit 126 maintains a state in which thefirst pulse signal P1 is “0”. Then, if the predetermined delay time Atpasses after the pulse signal P0 is “0”, the dead time generation unit126 maintains a state in which the second pulse signal P2 is “1”. Here,the pulse generation portion further includes a delay portion thatdeviates timing for outputting the pulse signal P1 to the first switchS1 and the pulse signal P2 to the second switch S2 so that the firstswitch S1 and the second switch S2 are not switched at the same time.

In this manner, according to the second embodiment, the first pulsesignal P1 and the second pulse signal P2 are not switched at the sametime by an operation of the dead time generation unit 126. Accordingly,it is possible to avoid a danger of switching on the first switch S1 andthe second switch S2 at the same time. In addition, it is obvious thatthe same effect according to the first embodiment described above can beobtained.

Third embodiment

Next, a third embodiment is described. In addition, according to thethird embodiment, portions common to the second embodiment are denotedby the same reference numerals, and the detailed descriptions thereofare omitted.

FIG. 8 is a diagram illustrating a circuit configuration of a powerconversion apparatus 1-3 according to the third embodiment. The powerconversion apparatus 1-3 includes a power conversion circuit 11-3 and acontroller 12-3 thereof. The power conversion circuit 11-3 furtherincludes a first capacitance voltage detection unit 15 and a secondcapacitance voltage detection unit 16 in addition to the powerconversion circuit 11-2 according to the second embodiment.

The first capacitance voltage detection unit 15 detects a potentialdifference generated between both ends of the first capacitor C1 as acapacitance voltage Vc1 (first capacitance voltage detection portion).The second capacitance voltage detection unit 16 detects potentialdifference generated between both ends of the second capacitor C2 as acapacitance voltage Vc2 (second capacitance voltage detection portion).The first and second capacitance voltage detection units 15 and 16respectively provide the detected capacitance voltages Vc1 and Vc2 tothe controller 12-1.

The controller 12-3 generates the first and second the pulse signals P1and P2 based on the circuit current Is, the supply voltage Vin, and thecapacitance voltages Vc1 and Vc2. Then, the controller 12-3 supplies thefirst pulse signal P1 to the first switch S1, and the second pulsesignal P2 to the second switch S2.

FIG. 9 is a block diagram illustrating a specific configuration of thecontroller 12-3. The controller 12-3 includes a capacitance voltagenegative feedback unit 127 in addition to the current target valuedecision unit 121, the envelope generation unit 122, the upperdetermination unit 123, the lower determination unit 124, the latchcircuit 125 and the dead time generation unit 126.

The capacitance voltage negative feedback unit 127 sets a coefficient kto be used in the current target value decision unit 121. That is, thecapacitance voltage negative feedback unit 127 inputs the capacitancevoltage Vc1 of the first capacitor C1 detected by the first capacitancevoltage detection unit 15 and the capacitance voltage Vc2 of the secondcapacitor C2 detected by the second capacitance voltage detection unit16. Then, the capacitance voltage negative feedback unit 127 determineswhether a total capacitance voltage Vc1+Vc2 obtained by adding thecapacitance voltage Vc1 and the capacitance voltage Vc2 is higher orlower than a first threshold value SH1, sets the coefficient k to be afirst value k1 when the total capacitance voltage Vc1+Vc2 is higher thanthe first threshold value SH1. In contrast, if the capacitance voltageis lower than a second threshold value SH2 which is lower than the firstthreshold value SH1, the capacitance voltage negative feedback unit 127sets the coefficient k to be a second value k2 which is smaller than thefirst value k1 (capacitance voltage negative feedback portion).

The current target value decision unit 121 receives a signal of thesupply voltage Vin detected by the supply voltage detection unit 14 asan input, multiplies the signal by the coefficient k (k1 or k2), anddecides the target current value It.

FIG. 10 is a diagram illustrating waveforms for describing an operationof the power conversion apparatus 1-3. In FIG. 10, a waveform Wrindicates the circuit current Is detected by the circuit currentdetection unit 13. In the circuit current Is, the high frequencycomponent (100 Hz) generated by the opening and the closing of the firstswitch S1 and the second switch S2 is mixed with the low frequencycomponent (50 Hz) in the same cycle with the supply voltage.

A waveform Ws indicates a current flowing to the AC power supply E afterthe circuit current Is passes through the low pass filter LPF. In orderto remove the high frequency component from the low pass filter LPF, acurrent only with the low frequency component of 50 Hz flows to the ACpower supply E.

In the operation circumstance as described above, when the inputelectric power is either increased or decreased, since the supplyvoltage Vin is common, an input current Iin may be increased ordecreased. In order to increase or decrease the input current Iin, thecoefficient k may be changed in a step of deciding the target currentvalue It by multiplying the waveform of the supply voltage Vin by thecoefficient k according to the first embodiment. For example, if thewaveform Ws is the target current value It and the peak of the currentvalue It is 2.82 A, the coefficient k is set to be great in order toincrease the input current Iin so that the peak becomes, for example,2.9 A. In contrary, in order to decrease the input current Iin, thecoefficient k is set to be small so that the peak becomes, for example,2.7 A.

A waveform Wt indicates a case in which the coefficient k is small, andwave motions of the low frequency component of 50 Hz are small. However,since the interval between the envelopes determined by the width d isnot changeable, the switching frequency of the high frequency component(100 KHz) reciprocating between the envelopes is hardly influenced. Ifthe switching frequency is not changed, the electric power consumed inthe load M driven as the inverter hardly changes. That is, only theinput electric power decreases without changing the output electricpower. Therefore, a relationship of “input electric power<outputelectric power” is eventually satisfied. Then, the electric charges ofthe first capacitor C1 and the second capacitor C2 are consumed. Thatis, the total capacitance voltage Vc1+Vc2 decreases.

Here, in the capacitance voltage negative feedback unit 127, if thetotal capacitance voltage Vc1+Vc2 decreases to be lower than the secondthreshold value SH2, the coefficient k is set to be the first value k1.As a result, since the wave motion of the target current value It isgreat, the input current Iin increases.

In a waveform Wu, the coefficient k is great, and the wave motion of thelow frequency component of 50 Hz is great. However, since the intervalbetween the envelopes defined by the width d is not changed, theswitching frequency of the high frequency component (100 KHz)reciprocating between the envelopes is hardly influenced. If theswitching frequency is not changed, the electric power consumed in theload M driven as the inverter hardly changes. That is, only the inputelectric power increases without changing the output electric power.Therefore, a relationship of “input electric power>output electricpower” is eventually satisfied. Then, the electric charges of the firstcapacitor C1 and the second capacitor C2 are accumulated. That is, thetotal capacitance voltage Vc1+Vc2 increases.

Here, if the total capacitance voltage Vc1+Vc2 becomes higher than thefirst threshold value SH1 (SH1>SH2), the capacitance voltage negativefeedback unit 127 sets the coefficient k to be the second value k2(k2<k1). As a result, since the wave motion of the target current valueIt becomes small, the input current Iin decreases.

In this manner, the total capacitance voltage Vc1+Vc2 obtained by addingthe capacitance voltage Vc1 of the first capacitor C1 and thecapacitance voltage Vc2 of the second capacitor C2 fluctuates accordingto the relationship in balance with the input electric power and theoutput electric power, that is, the electric power consumed in the loadM. Generally, since the impedance of the load M fluctuates, the consumedelectric power frequently fluctuates, and the total capacitance voltageVc1+Vc2 also fluctuates according to the change.

According to the third embodiment, the total capacitance voltage Vc1+Vc2is negatively fed back to the coefficient k when the target value of thecircuit current Is is decided. Specifically, if the total capacitancevoltage Vc1+Vc2 is high, the target value of the circuit current Isdecreases by setting the coefficient k to be small. In contrast, if thetotal capacitance voltage Vc1+Vc2 is low, the target value of thecircuit current Is is set to be high by setting the coefficient k to begreat. Accordingly, even if the impedance of the load M changes, thetotal capacitance voltage Vc1+Vc2 can be stably maintained.

According to the third embodiment, it is possible to control only theinput electric power by being separated from the output electric power(the consumed electric power of the load M). Accordingly, it is possibleto provide the power conversion apparatus 1-3 having a simpleconfiguration and good controllability. The simple configuration andeasy controllability are greatly advantageous in the industry.

In addition, according to the third embodiment, the relationship betweenthe first threshold value SH1 and the second threshold value SH2 is setto be [SH1>SH2], but the relationship may be [SH1=SH2].

Additionally, according to the third embodiment, through the capacitancevoltage negative feedback unit 127 is provided to the controller 12-2 ofthe second embodiment, but the capacitance voltage negative feedbackunit 127 may be provided to the controller 12-1 of the first embodiment.In this case, it is also possible to obtain the effect described in thethird embodiment.

Fourth Embodiment

Next, a fourth embodiment is described. According to the thirdembodiment, a case in which the input electric power is controlled bybeing separated from the output electric power (the consumed electricpower of the load M) is described. According to the fourth embodiment, acase in which an output current Tout (the electric current flowingthrough the load M) is controlled by being separated from the inputcurrent Iin (the electric current flowing through the AC power supply E)is further described. In addition, according to the fourth embodiment,the portions common to the third embodiment are denoted by the samereference numerals, and the detailed descriptions thereof are omitted.

A power conversion apparatus 1-4 according to the fourth embodimentincludes a power conversion circuit 11-4 and a controller 12-4 thereof.The power conversion circuit 11-4 has the same configuration as thepower conversion circuit 11-3 according to the third embodiment.

FIG. 11 is a block diagram illustrating a specific configuration of thecontroller 12-4. The controller 12-4 includes a circuit current negativefeedback unit 128 in addition to the current target value decision unit121, the envelope generation unit 122, the upper determination unit 123,the lower determination unit 124, the latch circuit 125, the dead timegeneration unit 126, and the capacitance voltage negative feedback unit127.

The circuit current negative feedback unit 128 receives the circuitcurrent Is as an input. Then, when the circuit current Is is greaterthan a third threshold value SH3, the circuit current negative feedbackunit 128 sets a coefficient j to be a value j1 smaller than “1”. Incontrary, if the circuit current Is is lower than a fourth thresholdvalue SH4 which is smaller than the third threshold value SH3, thecircuit current negative feedback unit 128 sets the coefficient j to bea value j2 greater than “1”. The circuit current negative feedback unit128 provides the coefficient j to the envelope generation unit 122.Here, the control portion configured with the controller 12-4 furtherincludes a circuit current negative feedback portion that adjusts theinterval between the envelope on the positive side and the envelope onthe negative side based on the value of the circuit current.

The envelope generation unit 122 obtains the product jd by multiplyingthe predetermined width d by the coefficient j. Then, the envelopegeneration unit 122 generates the positive envelope +e by adding theproduct jd to a signal corresponding to the target current value It.Additionally, the envelope generation unit 122 generates the negativeenvelope −e by subtracting the product jd from the signal correspondingto the current value It. Then, the envelope generation unit 122 suppliesthe signal corresponding to the positive envelope +e to the first inputterminal of the upper determination unit 123, and supplies the signalcorresponding to the negative envelope −e to the first input terminal ofthe lower determination unit 124.

The operations of the upper determination unit 123, the lowerdetermination unit 124, the latch circuit 125, and the dead timegeneration unit 126 are the same as those in the third embodiment.

FIG. 12 is a diagram illustrating waveforms for describing the operationof the power conversion apparatus 1-4. In FIG. 12, a waveform Wvindicates the circuit current Is that is detected by the circuit currentdetection unit 13. In the circuit current Is, the high frequencycomponent (100 Hz) generated by the opening and the closing of the firstswitch S1 and the second switch S2 is mixed with the low frequencycomponent (50 Hz) in the same cycle as the supply voltage.

A waveform Ww indicates a current flowing to the AC power supply E afterthe circuit current Is passes through the low pass filter LPF. Since thehigh frequency component is removed from the low pass filter LPF, acurrent only with the low frequency component of 50 Hz flows to the ACpower supply E.

In the operation circumstance as described above, if it is desired todecrease the current supplied to the load M, that is, a so-called outputcurrent Iout, that is, if the circuit current Is is increased, thecircuit current negative feedback unit 128 sets the coefficient j to bethe value j1 smaller than “1”. Then, as indicated by a waveform Wx, theinterval between the positive envelope +e and the negative envelope −ebecomes narrow. If the interval between the envelopes becomes narrow, acontrol is performed so that the circuit current Is reciprocates betweenthe envelopes, and the circuit current Is decreases. At the same time,the frequency of the high frequency component mixed with the circuitcurrent Is becomes high. Therefore, the output current Iout decreases.

In contrary, if it is desired to increase the output current Iout, thatis, the circuit current Is is decreased, the circuit current negativefeedback unit 128 sets the coefficient j to be the value j2 greater than“1”. Then, as indicated by a waveform Wy, the interval between thepositive envelope +e and the negative envelope −e becomes wide. If theinterval between the envelopes becomes wide, the circuit current Isincreases. At the same time, the frequency of the high frequencycomponent to be mixed in the circuit current Is decreases. Therefore,the output current Iout increases.

Meanwhile, the input current Iin changes to correspond to the waveformof a central line between the positive envelope +e and the negativeenvelope −e. Therefore, even if the interval between the envelopeschanges by multiplying the width d by the coefficient j, the wave motionof the input current Iin does not change. That is, the input current Iindoes not change. If the input current Iin does not change, the inputelectric power also does not change.

According to the fourth embodiment described above, it is possible tocontrol the output current Iout flowing to the load M by being separatedfrom the input current Iin flowing to the AC power supply E.Accordingly, it is possible to provide the power conversion apparatus1-4 having a simple configuration and good controllability to the loadM. The simple configuration and easy controllability are greatlyadvantageous in the industry.

In addition, according to the fourth embodiment, the relationshipbetween the third threshold value SH3 and the fourth threshold value SH4is set to be [SH3>SH4], but the relationship may be [SH3=SH4].

Additionally, according to the fourth embodiment, the circuit currentnegative feedback unit 128 is provided to the controller 12-3 of thethird embodiment, but the circuit current negative feedback unit 128 maybe provided to the controller 12-1 of the first embodiment or thecontroller 12-2 of the second embodiment. In this case, it is alsopossible to obtain the effect described in the fourth embodiment.

Fifth Embodiment

Next, a fifth embodiment is described. In the fourth embodiment, a casein which the output current Iout which is separated from the inputcurrent Iin is controlled is described. According to the fifthembodiment, a case in which a control is performed so that the voltageapplied to the load M is stably maintained. The control described abovegenerally is referred to as a voltage supply-type inverter control. Inaddition, according to the fifth embodiment, the portions common to thethird embodiment are denoted by the same reference numerals, and thedetailed descriptions thereof are omitted.

FIG. 13 is a diagram illustrating a circuit configuration of a powerconversion apparatus 1-5 according to the fifth embodiment. The powerconversion apparatus 1-5 includes a power conversion circuit 11-5 and acontroller 12-5 thereof. The power conversion circuit 11-5 includes aload voltage detection unit 17 in addition to the power conversioncircuit 11-3 of the third embodiment. The load voltage detection unit 17detects a potential difference generated between both ends of the load Mas a load voltage Vout. The load voltage detection unit 17 provides thedetected load voltage Vout to the controller 12-5. Here, the loadvoltage detection unit 17 configures a load voltage detection portionthat detects the potential difference generated between both ends of theload as a load voltage.

The controller 12-5 generates the first and second pulse signals P1 andP2 based on the circuit current Is, the supply voltage Vin, thecapacitance voltages Vc1 and Vc2, and the load voltage Vout. Then, thecontroller 12-5 supplies the first pulse signal P1 to the first switchS1, and the second pulse signal P2 to the second switch S2.

FIG. 14 is a block diagram illustrating a specific configuration of thecontroller 12-5. The controller 12-5 includes a load voltage negativefeedback unit 129 in addition to the current target value decision unit121, the envelope generation unit 122, the upper determination unit 123,the lower determination unit 124, the latch circuit 125, the dead timegeneration unit 126, and the capacitance voltage negative feedback unit127.

The load voltage negative feedback unit 129 receives the load voltageVout as an input. Even if the circuit current Is is constant, if theimpedance of the load M changes, the load voltage Vout fluctuates. Whenthe load voltage Vout is higher than a fifth threshold value SH5, theload voltage negative feedback unit 129 sets the coefficient j to be avalue j1 smaller than “1”. In contrary, if the load voltage Vout islower than a sixth threshold value SH6 which is smaller than the fifththreshold value SH5, the load voltage negative feedback unit 129 setsthe coefficient j to be a value j2 greater than “1”. The load voltagenegative feedback unit 129 provides the coefficient j to the envelopegeneration unit 122 (load voltage negative feedback portion). Here, thecontrol portion configured with the controller 12-5 further includes aload voltage negative feedback portion that adjusts an interval betweenthe envelope on the positive side and the envelope on the negative sidebased on the load voltage.

The envelope generation unit 122 obtains the product jd by multiplyingthe predetermined width d by the coefficient j. Then, the envelopegeneration unit 122 generates the positive envelope +e by adding theproduct jd to the signal corresponding to the target current value It.Additionally, the envelope generation unit 122 generates the negativeenvelope −e by subtracting the product jd from the signal correspondingto the current value It. Then, the envelope generation unit 122 suppliesthe signal corresponding to the positive envelope +e to the first inputterminal of the upper determination unit 123 and supplies the signalcorresponding to the negative envelope −e to the first input terminal ofthe lower determination unit 124.

The operations of the upper determination unit 123, the lowerdetermination unit 124, the latch circuit 125, and the dead timegeneration unit 126 are the same as those in the third embodiment.

The description of the operation of the power conversion apparatus 1-5can be provided with reference to the waveform diagram of FIG. 12without change. That is, when it is desired to decrease the voltageapplied to the load M, that is, when the load voltage Vout increases,the coefficient j is set to be the value j1 smaller than “1”. Then, theinterval between the positive envelope +e and the negative envelope −ebecomes narrow. If the interval between the envelopes is narrow, thevoltage applied to the load M decreases.

In contrary, when it is desired to increase the voltage applied to theload M, that is, when the load voltage Vout decreases, the coefficient jis set to be the value j2 greater than “1”. Then, the interval betweenthe positive envelope +e and the negative envelope −e becomes wide. Ifthe interval between the envelopes is wide, the voltage applied to theload M increases.

Meanwhile, the input current Iin changes to be correspond to thewaveform of the central line between the positive envelope +e and thenegative envelope −e. Therefore, even if the interval between theenvelopes changes by multiplying the width d by the coefficient j, thewave motion of the input current Iin does not change. That is, the inputcurrent Iin does not change. If the input current Iin does not change,the input electric power also does not change.

According to the fifth embodiment described above, a control may beperformed so that the voltage applied to the load M without changing theinput electric power is constant. This means that even if a high-speedresponse control is performed on the fast change of the load M, thisdoes not influence on the input current waveform. That is, since bothaspects of the high-speed responsiveness required to the fluctuation ofthe load and the constant control on the harmonics of the input currentare satisfied at the same time, the industrial effect is great.

In addition, according to the fifth embodiment, the relationship betweenthe fifth threshold value SH5 and the sixth threshold value SH6 is setto be [SH5>SH6], but the relationship may be [SH5=SH6].

Additionally, according to the fifth embodiment, the load voltagenegative feedback unit 129 is provided to the controller 12-3 of thethird embodiment, but the load voltage negative feedback unit 129 may beprovided to the controller 12-1 of the first embodiment or thecontroller 12-2 of the second embodiment. In this case, it is alsopossible to obtain the effect described in the fifth embodiment.

Sixth Embodiment

According to the first to fifth embodiments, in the operations of thepower conversion apparatuses 1-1 to 1-5, the total capacitance voltageVc1+Vc2 obtained by adding the capacitance voltage Vc1 of the firstcapacitor C1 and the capacitance voltage Vc2 of the second capacitor C2in the power conversion circuits 11-1 to 11-5 is constant. However, thecapacitance voltage Vc1 and the capacitance voltage Vc2 are graduallyseparated due to the fluctuations in the driving of the first and secondswitches S1 and S2 or the like. When the separation is great, there is aconcern that the voltage may exceed the withstand voltage in onecapacitor, and there is a concern that the voltage is too low in theother capacitor so that a circuit operation is not achieved. However,even in such cases, the total capacitance voltage Vc1+Vc2 does notchange. Therefore, the generation of the separation between thecapacitance voltage Vc1 and the capacitance voltage Vc2 may not bedetected by detecting the total capacitance voltage Vc1+Vc2. Then,according to the sixth embodiment, such a defect is resolved asdescribed below.

A power conversion apparatus 1-6 according to a sixth embodimentincludes a power conversion circuit 11-6 and a controller 12-6 thereof.The power conversion circuit 11-6 has the same configuration as thepower conversion circuit 11-5 according to the fifth embodiment.

FIG. 15 is a block diagram illustrating a specific configuration of thecontroller 12-6. The controller 12-6 includes an imbalance detectionunit 131 in addition to the current target value decision unit 121, theenvelope generation unit 122, the upper determination unit 123, thelower determination unit 124, the latch circuit 125, the dead timegeneration unit 126, the capacitance voltage negative feedback unit 127,and the load voltage negative feedback unit 129.

The imbalance detection unit 131 inputs the capacitance voltage Vc1detected by the first capacitance voltage detection unit 15 and thecapacitance voltage Vc2 detected by the second capacitance voltagedetection unit 16. Then, the imbalance detection unit 131 determineswhether a value Vc1−Vc2 obtained by subtracting the capacitance voltageVc2 from the capacitance voltage Vc1 is positive or negative. If thevalue Vc1−Vc2 is positive, the imbalance detection unit 131 provides apositive imbalance signal (+) to the current target value decision unit121. In contrary, if the value Vc1−Vc2 is negative, the imbalancedetection unit 131 provides a negative imbalance signal (−) to thecurrent target value decision unit 121. If the value Vc1−Vc2 is “0”, theimbalance signal is not provided to the current target value decisionunit 121 (imbalance detection portion).

When the positive imbalance signal (+) is received from the imbalancedetection unit 131, the current target value decision unit 121multiplies the coefficient k set by the capacitance voltage negativefeedback unit 127 by a predetermined coefficient h1. The coefficient h1is a value smaller than “1” when the supply voltage Vin is positive, andgreater than “1” when the supply voltage Vin is negative. The currenttarget value decision unit 121 decides the target current value It bymultiplying the signal of the supply voltage Vin by the coefficientk×h1. Then, the current target value decision unit 121 supplies thesignal corresponding to the current value It to the envelope generationunit 122.

In the same manner, when the negative imbalance signal (−) is receivedfrom the imbalance detection unit 131, the current target value decisionunit 121 multiplies the coefficient k set by the capacitance voltagenegative feedback unit 127 by a predetermined coefficient h2. Thecoefficient h2 is a value greater than “1” when the supply voltage Vinis positive, and smaller than “1” when the supply voltage Vin isnegative. The current target value decision unit 121 decides the targetcurrent value It by multiplying the signal of the supply voltage Vin bythe coefficient k×h2. Then, the current target value decision unit 121supplies the signal corresponding to the current value It to theenvelope generation unit 122.

In addition, if the positive or negative imbalance signal is notreceived, the current target value decision unit 121 uses thecoefficient k without change. That is, the current target value decisionunit 121 decides the target current value It by multiplying the signalof the supply voltage Vin by the coefficient k. Then, the current targetvalue decision unit 121 supplies the signal corresponding to the currentvalue It to the envelope generation unit 122.

The operations of the envelope generation unit 122, the upperdetermination unit 123, the lower determination unit 124, and the latchcircuit 125 are the same as the fifth embodiment.

FIG. 16 is a diagram illustrating waveforms in an example in which abalance between the capacitance voltage Vc1 of the first capacitor C1and the capacitance voltage Vc2 of the second capacitor C2 is disrupted.In FIG. 16, a waveform Wz is a waveform of the supply voltage Vin. Whenthere is no fluctuation in the driving of the first and second switchesS1 and S2, the capacitance voltage Vc1 of the first capacitor C1 and thecapacitance voltage Vc2 of the second capacitor C2 fluctuate bydeviating the phase by 180° as indicated in a waveform Waa. Therefore,in the operation of the power conversion apparatus 1-6, the totalcapacitance voltage Vc1+Vc2 is maintained to be constant.

However, if the fluctuation is generated in the driving of the first andsecond switches S1 and S2, the capacitance voltage Vc1 and thecapacitance voltage Vc2 may be gradually separated from each other asindicated in a waveform Wbb. However, even if the capacitance voltageVc1 and the capacitance voltage Vc2 are greatly separated from eachother, the total capacitance voltage Vc1+Vc2 is constant, and does notfluctuate.

FIG. 17 is a diagram illustrating waveforms for describing an operationwhen imbalance is generated since the capacitance voltage Vc1 of thefirst capacitor C1 is small and the capacitance voltage Vc2 of thesecond capacitor C2 is great. In FIG. 17, a waveform Wcc indicates atarget current value decided by the current target value decision unit121.

A broken line in FIG. 17 is a target current value It1 when there are nofluctuations between the capacitance voltage Vc1 and the capacitancevoltage Vc2, and a positive side and a negative side are symmetrical. Asolid line is a target current value It2 when there is a relationship[Vc1<Vc2] between the capacitance voltage Vc1 and the capacitancevoltage Vc2. That is, the solid line indicates a case in which the valueVc1−Vc2 obtained by subtracting the capacitance voltage Vc2 from thecapacitance voltage Vc1 is negative. In this case, the imbalancedetection unit 131 provides the negative imbalance signal (−) to thecurrent target value decision unit 121. Accordingly, the current targetvalue decision unit 121 multiplies the coefficient k by the coefficienth2. As a result, when the supply voltage Vin is positive, the wavemotion of the target current value It2 becomes great. In contrary, whenthe supply voltage Vin is negative, the wave motion of the targetcurrent value It2 becomes small.

The envelope generation unit 122 generates the positive envelope +e byadding the width d to the signal corresponding to the current value It2decided by the current target value decision unit 121. Additionally, theenvelope generation unit 122 generates the negative envelope −e bysubtracting the width d from the signal corresponding to the currentvalue It2. Then, the envelope generation unit 122 supplies the signalcorresponding to the positive envelope +e to the first input terminal ofthe upper determination unit 123, and supplies the signal correspondingto the negative envelope −e to the first input terminal of the lowerdetermination unit 124.

Therefore, as illustrated in the waveform Wdd in FIG. 17, the width ofthe amplitude does not change. However, the circuit current Is in whichwave motions when the supply voltage Vin is positive become differentfrom those when the supply voltage Vin is negative flows to the load M.As a result, when the supply voltage Vin is positive, the electriccharges which are charged in the first capacitor C1 increase, and whenthe supply voltage Vin is negative, the electric charges which aredischarged from the second capacitor C2 increase. Therefore, theimbalance between the capacitance voltage Vc1 and the capacitancevoltage Vc2 is resolved as a result.

FIG. 18 is a diagram illustrating waveforms for describing the operationwhen the imbalance is generated since the capacitance voltage Vc1 of thefirst capacitor C1 is great, and the capacitance voltage Vc2 of thesecond capacitor C2 is small. In FIG. 18, a waveform Wee indicates thetarget current value defined by the current target value decision unit121.

A broken line in FIG. 18 is the target current value It1 when there areno fluctuations between the capacitance voltage Vc1 and the capacitancevoltage Vc2, and a positive side and a negative side are symmetrical. Asolid line is a target current value It3 when there is a relationship[Vc1>Vc2] between the capacitance voltage Vc1 and the capacitancevoltage Vc2. That is, the solid line indicates a case in which the valueVc1−Vc2 obtained by subtracting the capacitance voltage Vc2 from thecapacitance voltage Vc1 is positive. In this case, the imbalancedetection unit 131 provides the positive imbalance signal (+) to thecurrent target value decision unit 121. Accordingly, the current targetvalue decision unit 121 multiplies the coefficient k by the coefficienth1. As a result, when the supply voltage Vin is positive, the wavemotion of the target current value It3 becomes small. In contrary, whenthe supply voltage Vin is negative, the wave motion of the targetcurrent value It3 becomes great.

The envelope generation unit 122 generates the positive envelope +eobtained by adding the width d to the signal corresponding to thecurrent value It3 decided by the current target value decision unit 121.Additionally, the envelope generation unit 122 generates the negativeenvelope −e by subtracting the width d from the signal corresponding tothe current value It2. Then, the envelope generation unit 122 suppliesthe signal corresponding to the positive envelope +e to the first inputterminal of the upper determination unit 123 and supplies the signalcorresponding to the negative envelope −e to the first input terminal ofthe lower determination unit 124.

Therefore, as illustrated in a waveform Wff in FIG. 18, the width of theamplitude does not change. However, the circuit current Is in which wavemotions when the supply voltage Vin is positive become different fromthose when the supply voltage Vin is negative flows to the load M. As aresult, when the supply voltage Vin is positive, the electric chargeswhich are discharged from the first capacitor C1 increase, and when thesupply voltage Vin is negative, the electric charges which are chargedin the second capacitor C2 increase. Therefore, the imbalance betweenthe capacitance voltage Vc1 and the capacitance voltage Vc2 is resolvedas a result.

In this manner, according to the sixth embodiment, since the capacitancevoltages Vc1 and Vc2 between the first capacitor C1 and the secondcapacitor C2 can be maintained in an appropriate scope, it is possibleto prevent the breakage of the capacitor due to the voltage exceedingthe withstand voltage, and the unstable circuit operation due to thelack of the voltage. Accordingly, since it is possible to maintain thebalance by a comparatively simple control, this can be easily used inthe industry.

In addition, according to the sixth embodiment, the imbalance detectionunit 131 is provided to the controller 12-5 of the fifth embodiment, butthe imbalance detection unit 131 may be provided to the controller 12-3of the third embodiment or the controller 12-4 of the fourth embodiment.In this case, it is also possible to obtain the effect described in thesixth embodiment.

Seventh Embodiment

Subsequently, the seventh embodiment is described. As described in thethird embodiment, when the input electric power is increased, thecoefficient k is set to be great by the function of the capacitancevoltage negative feedback unit 127. Then, the wave motion of the targetcurrent value It becomes great. Additionally, as described in the fourthembodiment, when the output electric power is decreased, a coefficient Jis set to be small by the function of the load voltage negative feedbackunit 129. Then, the interval between the positive envelope +e and thenegative envelope −e becomes narrow.

In FIG. 20, a waveform Wgg indicates the circuit current Is which is ina normal state. From the state, when the input electric power isincreased and also the output electric power is decreased, the wavemotion of the target current value It is increased by setting thecoefficient k to be great and also the interval between the envelopes isnarrowed by setting the coefficient J to be small, as described above.As a result, the envelope may enter a region in the opposite polarity.

In FIG. 20, the waveform Whh indicates the circuit current Is when thenegative envelope −e enters a positive region in a section T1, and thepositive envelope +e enters a negative region in a section T2. Positiveand negative values are repeated in the circuit current Is according tothe related art, but in this case, the circuit current Is continues tomaintain a positive value in the section T1 and continues to maintain anegative value in the section T2. Accordingly, since the circuit currentIs does not perform correct switching in the sections T1 and T2,electric power is excessively lost. According to the seventh embodiment,such a defect is resolved.

The power conversion apparatus 1-7 according to the seventh embodimentincludes a power conversion circuit 11-7 and a controller 12-7 thereof.The power conversion circuit 11-7 has the same configuration as thepower conversion circuit 11-6 according to the sixth embodiment.

FIG. 19 is a block diagram illustrating a specific configuration of thecontroller 12-7. The controller 12-7 includes first and second Zero VoltSwitching (ZVS) compensation units 132 and 133, in addition to thecurrent target value decision unit 121, the envelope generation unit122, the upper determination unit 123, the lower determination unit 124,the latch circuit 125, the dead time generation unit 126, thecapacitance voltage negative feedback unit 127, the load voltagenegative feedback unit 129, and the imbalance detection unit 131.

The first ZVS compensation unit 132 receives the positive envelope +egenerated by the envelope generation unit 122 as an input. Then, thefirst ZVS compensation unit 132 verifies whether the positive envelope+e is within a lower limit Amin in a positive region. If the positiveenvelope +e exceeds the lower limit Amin in the positive region, thefirst ZVS compensation unit 132 provides the positive envelope +e to theupper determination unit 123 without change. In contrary, if thepositive envelope +e is less than the lower limit Amin, the first ZVScompensation unit 132 unconditionally replaces the positive envelope +eto the lower limit Amin. That is, the first ZVS compensation unit 132provides the lower limit Amin to the upper determination unit 123 as thepositive envelope +e (first compensation portion).

The second ZVS compensation unit 133 receives the negative envelope −egenerated by the envelope generation unit 122 as an input. Then, thesecond ZVS compensation unit 133 verifies whether the negative envelope−e is within an upper limit Bmax in the negative region. If the negativeenvelope −e is less than the upper limit Bmax in the negative region,the second ZVS compensation unit 133 provides the negative envelope −eto the lower determination unit 124 without change. In contrary, if thenegative envelope −e exceeds the upper limit Bmax, the second ZVScompensation unit 133 unconditionally replaces the negative envelope −eto the upper limit Bmax. That is, the second ZVS compensation unit 133provides the upper limit Bmax to the lower determination unit 124 as thenegative envelope −e (second compensation portion).

The operations of the current target value decision unit 121, theenvelope generation unit 122, the capacitance voltage negative feedbackunit 127, the load voltage negative feedback unit 129, and the imbalancedetection unit 131 in the upstream of the first and second ZVScompensation units 132 and 133 and the upper determination unit 123, thelower determination unit 124, and the latch circuit 125 in thedownstream are the same as those in the sixth embodiment.

When the circuit current Is indicated by the waveform Whh of FIG. 20 isobtained, a waveform Wii in FIG. 20 is the circuit current Is after theZVS compensation is performed. As indicated by the waveform Wii, in thesection T1 in which the negative envelope −e exceeds the negative upperlimit Bmax, the second ZVS compensation unit 133 replaces the negativeenvelope −e to the negative upper limit Bmax. Therefore, the negativeenvelope −e does not enter the positive region.

In the same manner, in the section T2 in which the positive envelope +eis less than the negative lower limit Amin, the first ZVS compensationunit 132 replaces the positive envelope +e to the positive lower limitAmin. Therefore, the positive envelope +e does not enter the negativeregion.

Accordingly, since positive and negative values are always repeated inthe circuit current Is, when the first switch S1 or the second switch S2is switched on, the voltages on both ends of the switches S1 and S2 arealways zero. Therefore, it is possible to obtain the switching operationin which the loss of the electric power is extremely small.

In addition, according to the seventh embodiment, the first and secondZVS compensation units 132 and 133 are provided to the controller 12-6of the sixth embodiment, but the first and second ZVS compensation units132 and 133 may be provided to the controller 12-3, 12-4, and 12-5according to the third to fifth embodiments. In this case, it is alsopossible to obtain the effect described in the seventh embodiment.

Other Embodiments

The exemplary embodiments are not limited to the above.

For example, according to the embodiments, the single phase AC powersupply E is used, but the AC power supply E is not limited to the singlephase. It is possible to use a three phase AC power supply or apolyphase AC power supply of more than three phases.

Additionally, according to the embodiments, the high pass filter HPF isprovided in a path that bypasses the AC power supply E and the low passfilter LPF, but the high pass filter HPF may be omitted.

Additionally, according to the embodiments, MOS-type field effecttransistor is provided as an example of the first and second switches S1and S2, but the first and second switches S1 and S2 are not limitedthereto. For example, the first and second switches S1 and S2 may bebipolar transistors, or switches using semiconductor elements such asIGBT, GaN, and SiC. Otherwise, the first and second switches S1 and S2may be formed by combining a mechanical switch such as a relay and adiode.

What is claimed is:
 1. A power conversion apparatus comprising: a powerconversion circuit that includes a path configured to form a closed loopby connecting a first switch and a second switch in series, connecting afirst capacitor and a second capacitor in series, and connecting thefirst switch and the second switch respectively to the first capacitorand the second capacitor, to connect a connection point between thefirst switch and the second switch and a connection point between thefirst capacitor and the second capacitor through a series circuit of anAC power supply, a low pass filter, an inductor, and a load, and tobypass the AC power supply and the low pass filter; a circuit currentdetection portion adapted to detect a circuit current that flows throughthe power conversion circuit; a supply voltage detection portion adaptedto detect a voltage of the AC power supply; and a control portionadapted to output pulse signals for alternately opening and closing thefirst switch and the second switch to the first switch and the secondswitch based on the circuit current detected by the circuit currentdetection portion and a supply voltage detected by the supply voltagedetection portion so that a current in which a high frequency componentis mixed with a low frequency component of the AC power supply flows tothe power conversion circuit.
 2. The apparatus according to claim 1,wherein the control portion includes: a decision portion adapted todecide a target value of the current flowing through the powerconversion circuit based on a signal of the supply voltage detected bythe supply voltage detection portion; an envelope generation portionadapted to generate positive and negative envelopes having apredetermined width maintained to be the target value of the currentdecided by the decision portion; a determination portion adapted todetermine whether the circuit current detected by the circuit currentdetection portion is within a scope between the positive envelope andthe negative envelope; and a pulse generation portion adapted togenerate the pulse signal at a timing obtained by the determinationportion which determines that the circuit current is out of the scopebetween the positive envelope and the negative envelope.
 3. Theapparatus according to claim 2, further comprising: a first capacitancevoltage detection portion adapted to detect a potential differencegenerated between both ends of the first capacitor, as a firstcapacitance voltage; and a second capacitance voltage detection portionadapted to detect a potential difference generated between both ends ofthe second capacitor, as a second capacitance voltage, wherein thecontrol portion further includes a capacitance voltage negative feedbackportion adapted to adjust the target value of the current decided by thedecision portion based on the first capacitance voltage and the secondcapacitance voltage.
 4. The apparatus according to claim 3, wherein thecontrol portion further includes an imbalance detection portion adaptedto compare the first capacitance voltage and the second capacitancevoltage, and wherein when the imbalance detection portion detects thatthe first capacitance voltage is higher than the second capacitancevoltage, the decision portion sets the target value of the current to besmall if the supply voltage is positive and the target value of thecurrent to be great if the supply voltage is negative, and when theimbalance detection portion detects that the first capacitance voltageis lower than the second capacitance voltage, the decision portion setsthe target value of the current to be great if the supply voltage ispositive and the target value of the current to be small if the supplyvoltage is negative.
 5. The apparatus according to claim 3, wherein thecontrol portion further includes: a first compensation portion adaptedto set a lower limit of the positive envelope generated by the envelopegeneration portion in a positive region, and replace a value of thepositive envelope to the lower limit when the positive envelope is lessthan the lower limit, and a second compensation portion adapted to setan upper limit of the negative envelope generated by the envelopegeneration portion in a negative region, and replace a value of thenegative envelope to the upper limit when the negative envelope exceedsthe upper limit.
 6. The apparatus according to claim 4, wherein thecontrol portion further includes: a first compensation portion adaptedto set a lower limit of the positive envelope generated by the envelopegeneration portion in a positive region, and replace a value of thepositive envelope to the lower limit when the positive envelope is lessthan the lower limit, and a second compensation portion adapted to setan upper limit of the negative envelope generated by the envelopegeneration portion in a negative region, and replace a value of thenegative envelope to the upper limit when the negative envelope exceedsthe upper limit.